1. Field of the Invention
The present invention relates generally to techniques for determining and supporting required timing in communications systems. More particularly, the present invention relates to hardware reliant systems for automatically determining and supporting such timing.
2. Description of the Related Art
It is necessary quite often in communications systems to determine and support timing for data transfer. An example of such a circumstance involves the well-known approach for bidirectional communication known as the 1-Wire Protocol developed by Dallas Semiconductor Corporation. The 1-Wire Protocol effects half-duplex serial transfer within discrete time slots. In many cases, the 1-Wire Protocol is used for communication between a "cup shaped" master and a "button shaped" slave. In these cases a microcontroller (as the cup shaped master) initiates data transfer by sending a command word to the button-shaped slave "Touch Memory" portable data carrier.
According to the 1-Wire Protocol, commands and data are sent bit by bit to make bytes, starting with the least significant bit. FIG. 1 illustrates the general characteristics of the communication. The synchronization of master and slave is based on the sharp slope that the master generates by pulling the data line low. This sharp slope is generally indicated by reference numeral 2 (for a write one case) and by reference numeral 4 (for a write zero case) in FIG. 1. A certain time after this slope 2, 4, depending on data direction, either the master or the slave samples the voltage on the data line to get one bit of information. In FIG. 1, the period of time in which voltage may be sampled by the slave can be seen to reside between 15 microseconds after the sharp slope begins and 60 microseconds after that same event. Also, in FIG. 1, the period of time in which the master samples the line is less that 15 microseconds. That is to say, there is a 15 microsecond period before the line is pulled high in the write one case where a sampling would not result in a correct reading of a one; and further, there is a 60 microsecond limit on an active time slot before a next bit begins. The foregoing method of operation is called data transfer in time slots. Each time slot is independently timed so that communication pauses can occur between bits if necessary, without causing errors.
It has been found in practice that while the scheme described above and depicted in FIG. 1 provides a 45 microsecond window during which voltage can be sampled during a data transfer, many 1-Wire systems exist where virtually all sampling is done at about 30 microseconds after the sharp slope begins. In both systems having one slave and those having multiple slaves, it has been found rare in practice where sampling occurs much outside a range of about 27-33 microseconds after the line is first pulled low by the master to initiate and synchronize a bit. For example, whereas in theory master writing is limited by the maximum time of 60 microseconds (i.e., slowness could be a problem) and master reading is limited by the minimum time (i.e., fastness could be a problem), the fact remains that very little voltage sampling is done at the active time slot extremes.
It should be appreciated that maintaining a window of opportunity larger than is absolutely necessary reduces the speed of data transfer. It would be a tremendous advance in the art, therefore, to have a scheme in which the window of opportunity for voltage sampling is optimized, that is, made small enough so that accuracy is maintained, while obtaining marked improvements in speed of transfer.
Still further, recognizing the timing optimizing schemes can be effected in hardware, in software, or in a combination of the two, it should also be appreciated that it would be extremely desirable to have a scheme in which all components (whether hardware or software) are used efficiently and so to play to strengths.